Digital - Frontend & Backend
RTL Design & Verification
- We support Spec to Netlist for IP development and SoC development on ASIC or FPGA.
- Expertise in various IP development projects on Hardware-Accelerators, MIPI, Wireless protocols, USB, PCIE, DDR, Audio & Video Codecs etc.
- Our team has worked in SoC development for Consumer, Automotive and Aerospace (DO-254 standards) applications.
- Micro Architecture & RTL Development
- Low power design implementation
- SOC/Subsystem integration
- RTL QC Checks like LINT, CDC
- Timing Constraints, Synthesis, STA, LEC
- UPF, CLP
IP Verification & Validation
- Test feature extraction and test plan creation
- Functional coverage matrix to get maximum cross-functional verification
- Complete Verification Environment built up from scratch
Multicore SoC Verification
- SoC level verification and expertise in System Architecture to take up SoC verification
- Expertise in various processors from RISC based, DSP & Crypto processor cores
- Experience in various complex Protocols and Standards such as USB, Ethernet, PCIE, Wireless, DO-254
- Experience in Power architecture and UPF flow simulation.
- GLS flow setup with different tools and debug.
- X propagation clean up and debug
- Gate Level Simulation sign-off
DFT – Design for Testability
- DFT Implementation – Test Pin-Muxing, SCAN Insertion, LBIST Insertion, Compression
- Logic Insertion, Boundary Scan Insertion, Memory BIST insertion and IOs.
- Automatic Test Pattern Generation (ATPG), ATPG verification.
- DFT simulations and timing for SCAN, Boundary SCAN, MBIST & LBIST modes.
Physical Design, Verification and Sign Off:
- We have expertise in taking full ownership of RTL to GDS for Block Level or Top Level.
- We have three successful Tape Outs with full ownership where we built the entire Back End flow and delivered from Netlist to GDSII. One project was delivered in turnkey mode for a China client.
- Our Physical Design team has expertise in technology process nodes from 7nm FINFETs to 350nm BCDMOS.
- Setting up the synthesis flow
- Verifying constraints
- Different logic/timing/power optimization techniques
Static Timing Analysis (STA)
- Setting up the STA flow
- Develop timing constraints and exceptions
- Timing Analysis for multi modes & multi corners
- Timing ECOs using TSO or manual for timing critical paths
Physical Design & Verification
- Setting up the Physical Design Flow
- Floor Planning at Top Level & Block Level
- Power Planning at Top Level & Block Level
- Placement and optimization
- Clock Tree Synthesis (CTS)
- Routing and optimization
Logic Equivalence Check (LEC)
- Setting up the LEC flow for both functional and CLP
- Develop constraints
- Analysis & Debug
- Power Integrity (Power EM and IR-Drop)
- Signal Integrity (Sig EM, IR-Drop and Noise)
- Physical Verification (DRC, LVS, ERC, Customer Specific Checks)
FPGA Emulation and Prototyping
- Providing prototyping services for early software development and high-performance system validation
- Setting up the configurations and environment settings for emulation platforms
- Bringing up software on emulated full-chip SoC model with expertise in debugging and validation of software-hardware interaction
- Analysis and validation of design’s power and performance targets